The use of PLLs in communications over the years has become an ever-growing trend. New applications with specific synchronization requirements demand complex and flexible PLLs. Economic and integration reasons are pushing for support for multiple application scenarios, each requiring different standards employing different synchronization clock criteria. User configurable flexibility has become essential part of the design of new PLLs.
In a hierarchical timing network, it is desirable to place inexpensive equipment on line cards at the edge of the network. Wander and jitter filtering is then performed further up the timing chain by fewer timing cards with higher quality oscillators. This approach works well when the system is configured in a cascaded fashion, as shown in FIG. 1, with the output of one PLL feeding the input of the next. As long as the bandwidth of the line card PLL1 is much higher than the timing card PLL2, the overall system transfer function will be defined by timing card PLL2 transfer function.
A typical prior art arrangement is shown in FIG. 2. It comprises a separate timing card 10 and line card 12 for use with a timing-over-packet (ToP) system. The line card 12 comprises PLL1 14 and a time stamping physical interface (PHY) 16. The timing card 10 comprises PLL2 18, which includes a numerically controlled oscillator (NCO). PLL1 refers to the PLL the input clock recovered by the clock recovery module 20 and PLL2 generates the final output clock and feedback signals for both PLLs. Clock recovery module 20, is placed on the timing card 10 and runs a suitable recovery algorithm such as the IEEE 1588 protocol. This arrangement requires a complex data interface between the two cards 10, 12 to transfer time stamps and other connection data.
There are various types of His, broadly segregated into Type I PLLs and Type II PLLs. A typical PLL system contains an integrator and a proportional path in its loop filter. The type of the PLL can be defined based on number of integrator in its loop filter. For example a type I PLL does not contain an integrator in its loop filter transfer function, whereas a type II PLL does contain an integrator in its loop filter transfer function and is therefore of second order.